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Three stages amplifier college project help

Hi all
I’m designing my first 3 stages voltage amplifier as an electronics college course project.

Only BJT transistors present in LTSpice list are allowed.
Differential pair + common emitter stage + output stage.
Negative feedback.
As simple as possible. It is a simulation not followed by the real world implementation of it.

+-16V power supply
+- 175mV input signal swing corresponding to +- 14V output swing. (closed loop voltage gain = 80).
open loop gain of the 3 stages ampli = 2450 at least
resistive load >= 10ohm
amplifier input resistence >= 10kohm
bandwidth >=80 kHz
phase margin 80°
efficiency >=60%
THD <=1% I’ve started from the last stage.
I’ve chosen Sziklai configuration (I hope it’s not an overkill for this project).
I thought that after it was completed I could progress with the CE stage…
Unfortunately I’ve done something wrong and I’ve lost the biasing. I don’t know how to progress… I thought that giving Q2 Ib= Ic/beta (read in the LTSpice model specifatios) would give me the conditions prior to the CE insertion but I was wrong… What do I have to do? Can someone please help me?

Attached Files
File Type: asc 12-27-output-gain.asc (3.2 KB)
File Type: asc 12-27-output_circuit_sziklai.asc (2.7 KB)

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Three stages amplifier college project help

Hi all
I’m designing my first 3 stages voltage amplifier as an electronics college course project.

Only BJT transistors present in LTSpice list are allowed.
Differential pair + common emitter stage + output stage.
Negative feedback.
As simple as possible. It is a simulation not followed by the real world implementation of it.

+-16V power supply
+- 175mV input signal swing corresponding to +- 14V output swing. (closed loop voltage gain = 80).
open loop gain of the 3 stages ampli = 2450 at least
resistive load >= 10ohm
amplifier input resistence >= 10kohm
bandwidth >=80 kHz
phase margin 80°
efficiency >=60%
THD <=1% I’ve started from the last stage.
I’ve chosen Sziklai configuration (I hope it’s not an overkill for this project).
I thought that after it was completed I could progress with the CE stage…
Unfortunately I’ve done something wrong and I’ve lost the biasing. I don’t know how to progress… I thought that giving Q2 Ib= Ic/beta (read in the LTSpice model specifatios) would give me the conditions prior to the CE insertion but I was wrong… What do I have to do? Can someone please help me?

Attached Files
File Type: asc 12-27-output-gain.asc (3.2 KB)
File Type: asc 12-27-output_circuit_sziklai.asc (2.7 KB)

Continue reading at DIYaudio.com: Click Here

Press Release Distribution Service

Three stages amplifier college project help

Hi all
I’m designing my first 3 stages voltage amplifier as an electronics college course project.

Only BJT transistors present in LTSpice list are allowed.
Differential pair + common emitter stage + output stage.
Negative feedback.
As simple as possible. It is a simulation not followed by the real world implementation of it.

+-16V power supply
+- 175mV input signal swing corresponding to +- 14V output swing. (closed loop voltage gain = 80).
open loop gain of the 3 stages ampli = 2450 at least
resistive load >= 10ohm
amplifier input resistence >= 10kohm
bandwidth >=80 kHz
phase margin 80°
efficiency >=60%
THD <=1% I’ve started from the last stage.
I’ve chosen Sziklai configuration (I hope it’s not an overkill for this project).
I thought that after it was completed I could progress with the CE stage…
Unfortunately I’ve done something wrong and I’ve lost the biasing. I don’t know how to progress… I thought that giving Q2 Ib= Ic/beta (read in the LTSpice model specifatios) would give me the conditions prior to the CE insertion but I was wrong… What do I have to do? Can someone please help me?

Attached Files
File Type: asc 12-27-output-gain.asc (3.2 KB)
File Type: asc 12-27-output_circuit_sziklai.asc (2.7 KB)

Continue reading at DIYaudio.com: Click Here

Press Release Distribution Service

Three stages amplifier college project help

Hi all
I’m designing my first 3 stages voltage amplifier as an electronics college course project.

Only BJT transistors present in LTSpice list are allowed.
Differential pair + common emitter stage + output stage.
Negative feedback.
As simple as possible. It is a simulation not followed by the real world implementation of it.

+-16V power supply
+- 175mV input signal swing corresponding to +- 14V output swing. (closed loop voltage gain = 80).
open loop gain of the 3 stages ampli = 2450 at least
resistive load >= 10ohm
amplifier input resistence >= 10kohm
bandwidth >=80 kHz
phase margin 80°
efficiency >=60%
THD <=1% I’ve started from the last stage.
I’ve chosen Sziklai configuration (I hope it’s not an overkill for this project).
I thought that after it was completed I could progress with the CE stage…
Unfortunately I’ve done something wrong and I’ve lost the biasing. I don’t know how to progress… I thought that giving Q2 Ib= Ic/beta (read in the LTSpice model specifatios) would give me the conditions prior to the CE insertion but I was wrong… What do I have to do? Can someone please help me?

Attached Files
File Type: asc 12-27-output-gain.asc (3.2 KB)
File Type: asc 12-27-output_circuit_sziklai.asc (2.7 KB)

Continue reading at DIYaudio.com: Click Here

Press Release Distribution Service
Feature your business, services, products, events & news. Submit Website.